1. Field of the Invention
The present invention relates to error correction devices, and particularly to an error correction device which corrects an error in a string of symbols supplied via a data transmission line.
2. Description of the Background Art
In the field of digital communication, FEC (Forward Error Correction) technique using the, Reed-Solomon code has been employed as a technique for reducing errors which occur in a data transmission line.
FIG. 14 is a block diagram illustrating an error correction device of a receiver employing the FEC technique. Referring to FIG. 14, a code xcfx8631 which is demodulated by a demodulator (not shown) is supplied to a synchronization control unit 31. Code xcfx8631 includes a plurality of code blocks each including a plurality of symbols, and a leading symbol is used as a synchronization code (see FIG. 2). The synchronization code has a predetermined data value.
Referring to FIG. 15, synchronization control unit 31 includes an FIFO unit 40 which delays code xcfx8631 by one code block, and an equal/unequal detection unit 41 which detects whether or not a data value of an input symbol of FIFO unit 40 equals to a data value of an output symbol thereof and outputs an equality detection signal xcfx8641 if those values are equal to each other. Equality detection signal xcfx8641 is output when a synchronization code of a code block and a synchronization code of a following code block are respectively located at an input portion and an output portion of FIFO unit 40. Based on equality detection signal xcfx8641, a clock signal synchronized with the code block is generated, and the clock signal is supplied to the entire error correction device.
Code xcfx8631 passed through synchronization control unit 31 is de-interleaved by a de-interleaver 32 and supplied to a chain search operation unit 36 via an FIFO and FILO unit 35 and to a syndrome operation unit 33. Data obtained by syndrome operation unit 33 is supplied to an Euclidean operation unit 34 and data obtained by Euclidean operation unit 34 is supplied to chain search operation unit 36.
An output symbol string of FIFO and FILO unit 35 is subjected to an error correction process by chain search operation unit 36. The symbol string which has undergone the error correction process is input to a de-randomizer 38 via a FILO unit 37, de-randomized by de-randomizer 38 and then transmitted to any circuit in the following stage.
FIG. 16 illustrates a problem of the error correction device shown in FIG. 14. Referring to FIG. 16, the axis of abscissas represents C/N (db) in the data transmission line, where the noise of the transmission line becomes lower in the direction of the arrow (to the right). The axis of ordinates represents the bit error rate of a transmission and reception system, where the bit error rate becomes higher in the direction of the arrow (toward the top).
The curve E represents a relation between the C/N and the bit error rate of a system which does not employ the FEC technique. It can be found by curve E that the bit error rate becomes higher as the noise of the data transmission line increases.
The curve F represents a relation between the C/N and the bit error rate of a system which employs the FEC technique. As shown by curve F, it can be found that the system employing the FEC technique has a lower bit error rate in the region xe2x80x9cbxe2x80x9d where the noise in the data transmission line is relatively low. However, in the region xe2x80x9caxe2x80x9d where the noise in the data transmission line is relatively high, the system employing the FEC technique has a higher bit error rate. The reason is that the error correction device often fails to normally perform the correction process if the noise in the data transmission line exceeds a certain level.
One object of the present invention is to provide an error correction device having a low bit error rate.
According to one aspect of the invention, the error correction device includes a delay circuit which delays a symbol string which has not been subjected to error correction, and a delay circuit which delays a symbol string which has been subjected to error correction. If the error correction is not normally done, an output symbol string of the former delay circuit is supplied to a circuit in a following stage. If the error correction is normally done, an output symbol string of the latter delay circuit is supplied to the circuit in the following stage. Accordingly, the bit error rate is decreased compared with conventional error correction devices which supply to a circuit in a following stage a symbol string which has undergone error correction whether or not the error correction is normally performed.
According to another aspect of the invention, an error correction device includes a delay circuit which delays a symbol string which has been subjected to error correction and a holding circuit which holds the number of a symbol subjected to error correction and a data value thereof before correction. If the error correction is normally done, an output symbol string of the delay circuit is directly supplied to a circuit in a following stage. If the error correction is not normally done, a data value of an erroneously corrected symbol in the output symbol string of the delay circuit is re-corrected to the data value before correction, and the re-corrected symbol string is supplied to the circuit in the following stage. Accordingly, the bit error rate is decreased compared with conventional error correction devices which supply to a circuit in a following stage a symbol string which has undergone error correction whether or not the error correction is normally carried out.
According to still another aspect of the invention, an error correction device includes a delay circuit which delays a symbol string which has been subjected to error correction, a holding circuit which holds the number of a symbol subjected to error correction, a data value thereof, and a data value used for the correction, and an arithmetic operation circuit which determines a data value before correction based on the data value after the correction and the data value used for the correction that are held by the holding circuit. If the error correction is normally done, an output symbol string of the delay circuit is directly supplied to a circuit in a following stage. If the error correction is not normally done, a data value of a symbol of an erroneously corrected signal in the output symbol string of the delay circuit is re-corrected to the data value before the correction determined by the arithmetic operation circuit, and the re-corrected symbol string is supplied to the circuit in the following stage. Accordingly, the bit error rate is decreased compared with conventional error correction devices which supply to a circuit in a following stage a symbol string which has undergone error correction whether or not the error correction is normally made.
Preferably, each symbol string includes a predetermined number N of symbols, the leading symbol of each symbol string is used as a synchronization code, and a synchronization control circuit is further provided. The synchronization control circuit detects a symbol having a data value which is the same as that of the synchronization code. If the Nth symbol counted from a symbol next to the detected symbol is the synchronization code, the Nth symbol is determined as the leading symbol. The conventional FIFO unit is unnecessary in this case, and the circuit scale accordingly decreases.
Still preferably, the synchronization control circuit determines whether the Nth symbol counted from a symbol next to the symbol determined as the leading symbol has the same data value as that of the synchronization code. The circuit counts the number of positive results A and negative results B of the determination. If the ratio of positive results A to the total number of determinations A+B, i.e. A/(A+B) exceeds a predetermined threshold, a data value of a symbol with the negative result is corrected to the data value of the synchronization code. In this case, the error in the leading symbol is also corrected and the bit error rate is further decreased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.